With recent semiconductor memories such as SRAMs (Static Random. Access Memory), advanced CMOS process technologies for SoC applications have led to a reduction in the processing dimensions (scaling sizes) of integrated circuits, which in turn has led to higher chip density, lower chip cost, and increased memory capacity.
Such a reduction in the scaling size causes increased variation in the threshold voltage of transistors including SRAMs and other memory cells, reduced read/write noise margins from/to memory cells, destabilized memory cell operation, and increased bit error rate (BER; Bit Error Rate).
FIG. 1 is a graph relating the process technology node to the operating voltage of CMOS transistors in CMOS transistors. As the scaling size decreases, that is, miniaturization of the process technology node advances, the applied voltage VDD decreases. However, as shown in the dotted frame in the graph, the process technology node advancing 65 (nm) or smaller allows a voltage drop limit due to process variation. This is for the reason that as miniaturization of the process technology node advances, systematic factors such as manufacturing processes and memory cell locations and/or process variations in operating environments such as temperature environments and soft errors caused by cosmic rays increase the variation in the threshold value and thereby the reliability of CMOS transistors is reduced, resulting in an increase in the minimum operating voltage Vmin of CMOS transistors.
It is therefore a very important issue for advanced micro-VLSIs to operate at a low voltage. For lower power consumption and higher reliability, there is a need to stabilize the operation of memory cells including CMOS transistors.
Under such circumstances described above, the inventors had already proposed a novel semiconductor memory in which the bit reliability of memory cells can be varied dynamically according to applications and memory states to secure operation stability and achieve lower power consumption and higher reliability. The semiconductor memory provides dynamic switching between a mode in which one bit is allocated to one memory cell (1-bit/1-cell mode: hereinafter referred to as “normal mode”) and a mode in which one bit is allocated to n (where n is two or more) coupled memory cells (1-bit/n-cell mode: hereinafter referred to as “high-reliability mode”). Switching from the normal mode to the high-reliability mode enhances the operation stability of one bit, increases the cell current during read operations (for faster readout), and allows bit errors to be self-corrected (see Patent Document 1, for example).
FIG. 2 shows an embodiment of the proposed semiconductor memory, including memory cells each in turn including a pair of cross-couple connected inverters with the respective outputs connected to paths leading to a pair of respective bit lines disposed in correspondence to a column of the memory cells, a pair of switch units disposed between the bit lines and the outputs of the inverters, and a single word line for controlling the conduction of the switch units. In the thus arranged semiconductor memory, a pair of P-type MOS transistors and a single mode control line for controlling the P-type MOS transistors to be in conduction are further added between data holding nodes of two adjacent memory cells.
The circuit behavior of the memory cells shown in FIG. 2 will now be described briefly.
The memory cell (MC01) shown in FIG. 2 forms a latch circuit including a P-type MOS transistor (M00) and an N-type MOS transistor (M02) connected in series between a power supply potential VVDDA and a ground potential VGNDA and a P-type MOS transistor (M01) and an N-type MOS transistor (M03) connected in series between the power supply potential VVDDA and the ground potential VGNDA. The memory cell (MC01) itself employs a common 6-transistor configuration.
Similarly, the memory cell (MC10) forms a latch circuit including a P-type MOS transistor (M10) and an N-type MOS transistor (M12) connected in series between a power supply potential VVDDB and a ground potential VGNDB and a P-type MOS transistor (M11) and an N-type MOS transistor (M13) connected in series between the power supply potential VVDDB and the ground potential VGNDB. The memory cell (MC10) itself also employs a common 6-transistor configuration.
In the memory cell (MC01), the gate terminals of the P-type MOS transistor (M00) and the N-type MOS transistor (M02) are both connected to a node (N01) of the P-type MOS transistor (M01) and the N-type MOS transistor (M03). Also, the gate terminals of the P-type MOS transistor (M01) and the N-type MOS transistor (M03) are both connected to a node (N00) of the P-type MOS transistor (M00) and the N-type MOS transistor (M02). The transistors M00 to M03 are thus cross-couple connected, and the P-type MOS transistors (M00 and M01) operate as load transistors, while the N-type MOS transistors (M02 and M03) operate as drive transistors. The same applies to the memory cell (MC10).
The memory cell (MC01) also includes N-type MOS transistors (M04 and M05) as switch units connected, respectively, between complementary bit lines (BL and /BL) and the nodes (N00 and N01). The gate terminals of the N-type MOS transistors (M04 and M05) are both connected to a common word line (WLA), and gate potentials of the N-type MOS transistors (M04 and M05) are controlled through the word line (WLA). That is, in the memory cell (MC01), the P-type MOS transistors (M00 and M01) operate as load transistors, while the N-type MOS transistors (M02 and M03) operate as drive transistors, and the N-type MOS transistors (M04 and M05) operate as switch units.
The memory cell (MC10) also includes N-type MOS transistors (M14 and M15) as switch units connected, respectively, between the complementary bit lines (BL and /BL) and the nodes (N10 and N11). The gate terminals of the N-type MOS transistors (M14 and M15) are both connected to the common word line (WLA), and gate potentials of the N-type MOS transistors (M14 and M15) are controlled through the word line (WLA).
A pair of P-type MOS transistors (M20 and M21) are provided as mode control switch units between the data holding nodes (between N00 and N10 and between N01 and N11) of the memory cells (MC01 and MC10), and a single mode control line (/CTRL) for controlling the conduction of the P-type MOS transistors (M20 and M21) is provided.
In the thus arranged memory cells with such a circuit configuration, it is possible, using the mode control line (/CTRL), to separately use storing 1-bit data in the memory cell (MC01) and storing 1-bit data in the two memory cells (MC01 and MC10). The memory cells with such a circuit configuration have two states: a mode (normal mode) in which one bit is allocated to one memory cell and a mode (high-reliability mode) in which one bit is allocated to two coupled memory cells, whereby the bit reliability of the memory cells can be varied dynamically according to applications and memory states to secure operation stability and achieve lower power consumption and higher reliability.
As shown in FIG. 3, switching between the normal mode in which one bit is allocated to one memory cell and the high-reliability mode in which one bit is allocated to two coupled memory cells has conventionally been controlled at the level of memory cell blocks. Uniform switching control of the operating modes for each memory block, however, suffers from a problem of inhibiting achievement of lower operating voltage due to process variation.
On the other hand, known low-voltage cache memories and the like have eliminated factors inhibiting achievement of lower operating voltage of memory cells due to process variation, that is, have a created failure word map and use memories excluding failure words to achieve lower operating voltage.
As shown in FIG. 4, this is arranged such that four failure words (having a smaller operating margin) are preliminarily identified in one physical cache line (eight words form one cache line in FIG. 4), a failure word map (e.g. 01010011) is created, and a logic circuit is used to prepare one-half logic cache line using four failure-free words (having a larger operating margin). Similarly, four failure words are created in another physical cache line and a logic circuit is used to prepare one-half logic cache line using four failure-free words (having a larger operating margin).
Next, as shown in FIG. 5, the two one-half logic cache lines are joined to prepare one logic cache line. All the words forming this one logic cache line have a larger operating margin and thereby making it operable at a low voltage.
However, such a technique of joining two one-half logic c ache lines to prepare one logic cache line inevitably cuts the cache memory capacity and the association in half.    [Patent Document 1] WO2009/088020